The present invention relates generally to packaged semiconductor devices and, more particularly, to interposers for such devices.
An interposer is a component used in packaged semiconductor devices to route signals between ball grid arrays (BGAs) having different pitches.
FIG. 1 is a simplified, cross-sectional, side view of a conventional 2.5D (i.e., “2.5-dimensional”) packaged semiconductor device 100 mounted on a circuit board 126. The packaged device 100 has two adjacent integrated circuit (IC) dies 102 mounted on and electrically interconnected with an interposer 110 via corresponding micro-bump ball grid arrays (BGAs) 104. The interposer 110 is, in turn, mounted onto and electrically interconnected with a system-in-package (SiP) substrate 122 via a corresponding flip-chip bump BGA 120. Similarly, the SiP substrate 122 is, in turn, mounted on and electrically interconnected with the circuit board 126 by way of a corresponding package bump BGA 124.
As represented in FIG. 1, the pitch of the micro-bump BGAs 104 between the dies 102 and the interposer 110 is smaller than the pitch of the flip-chip bump array 120 between the interposer 110 and the SiP substrate 122. To provide the signal fan-out associated with those two different pitches, the interposer 110 has a silicon or glass substrate 114 containing metal through-silicon vias (TSVs) 118 that provide electrical interconnections between metal features formed in top-side metal layers 112 on the top side of the substrate 114 and back-side metal layers 116 on the back side of the substrate 114. The metal features formed in the top-side and back-side metal layers 112 and 116 include bump pads (not explicitly shown) for the solder bumps of the BGAs 104 and 120 as well as re-distribution layer (RDL) traces (not explicitly shown) on either or both of the substrate sides that route signals horizontally to provide the signal fan-out.
Conventional 2.5D interposers, such as the interposer 110 of FIG. 1, having a glass or silicon substrate, are manufactured using a relatively expensive, wafer fabrication process involving masking, exposure, etching, and metallization steps to form the TSVs within the substrate. Accordingly, it would be advantageous to have a less expensive interconnect structure.